I turn noisy signals into decisions.

At Edgepoint Infrastructure I keep the operational data behind Malaysia’s telecom-tower estate clean, and I automate the parts that shouldn’t need a person. Most of it is small, local Python—ETL scripts, Selenium jobs, an OCR pipeline—wired into proprietary systems and surfaced in Power BI for management.

The recurring pattern: find a manual process that leaks errors, model it, and replace it with something measured.

Unified memory architecture puts every processor on a chip—the CPU, the GPU, whatever accelerators sit alongside them—on one physical pool of RAM, under one address space. No processor keeps a private bank the others can’t reach.

What it removes is the copy. In a discrete design the GPU has its own VRAM, so using a buffer on both sides means shipping it across a bus—PCIe, NVLink—which costs time, bandwidth and energy, and forces you to size each pool up front. Under unified memory, the buffer the CPU wrote is already where the GPU reads it.

Give every core its own L1 (split into instruction and data) and a private L2 for speed—which every modern CPU does—and the moment two cores cache the same line you have a consistency problem: one writes it, the other must not keep reading the old value.

The fix is a coherence protocol—MESI and its relatives— coordinated through the last-level cache. Each LLC slice keeps a directory of which cores hold which lines, so a core that wants to write sends a read-for-ownership to the line’s home slice; the directory invalidates only the cores that actually have it, waits for their acknowledgements, then hands over the line. It works, but every write to shared data becomes a small round trip across the interconnect, and the traffic grows with how much the cores share—which is exactly what a unified pool encourages.